Read e-book online Advanced Test Methods for SRAMs: Effective Solutions for PDF

January 31, 2018 | Nanotechnology | By admin | 0 Comments

By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel

ISBN-10: 1441909370

ISBN-13: 9781441909374

ISBN-10: 1441909389

ISBN-13: 9781441909381

Advanced try tools for SRAMs: potent recommendations for Dynamic Fault Detection in Nanoscaled Technologies

by:

Alberto Bosio

Luigi Dilillo

Patrick Girard

Serge Pravossoudovitch

Arnaud Virazel

Modern electronics will depend on nanoscaled applied sciences that current new demanding situations when it comes to checking out and analysis. thoughts are really liable to defects seeing that they take advantage of the expertise limits to get the top density. This ebook is a useful advisor to the checking out and analysis of the newest new release of SRAM, some of the most prevalent form of thoughts. Classical tools for checking out reminiscence are designed to address the so-called "static faults", yet those attempt strategies aren't adequate for faults which are rising within the most up-to-date Very Deep Sub-Micron (VDSM) applied sciences. those new faults, often called "dynamic faults", aren't coated by way of classical algorithms and require the devoted try out and prognosis recommendations offered during this book.

  • First booklet to offer whole, cutting-edge assurance of dynamic fault checking out for SRAM memories;
  • Presents content material utilizing a "bottom-up" strategy, from the learn of factors of malfunctions as much as the iteration of shrewdpermanent try out ideas;
  • Includes case reports overlaying all reminiscence parts (core-cells, deal with decoders, write drivers, feel amplifiers, etc.);
  • Proposes an exhaustive research of resistive-open defects in every one reminiscence part and the ensuing dynamic fault modeling.

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Extra resources for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

Example text

1 depicts the typical six-transistor SRAM core-cell in CMOS technology. The circuit consists of a flip-flop based on two cross-coupled inverters and two access transistors Mtn3 and Mtn4. The access transistors are turned ON when the word line signal is selected (WLS at VDD), and they connect the flip-flop to the bit lines BL and BLB. Note that both bit lines BL and BLB are used for read/write purpose. The access transistors act as transmission gates allowing bi-directional current flow between the flip-flop and the bit lines.

Among these faults there are the static faults TFs and IRFs that are induced by defects Df1, Df5, and Df6. As described in Borri et al. (2005), the best sequence to detect the static faults RDFs and DRDFs (involved by defect Df2 and Df3) is 0w1r1. ’ Another r0 is needed to observe the fault. , March Y (Van de Goor 1998). As done for the test of dRDF due to defect Df4, the effect of RES can be used making the modified March C- able to produce the needed sequence to exhaustively cover all core-cell static faults.

BL BLB VDD Mtp1 Mtp2 PrecB Fig. 1 Two transistor pre-charge circuit As mentioned above, the memory array contains a pre-charge circuit for each couple of BL/BLB, as it can be observed in Fig. 2 that depicts a portion of an SRAM array. When a read operation is acted on a certain core-cell, the pre-charge circuit is turned OFF in the column of the selected core-cell. Thus, just before the core-cell selection, the bit lines have been charged and are floating at VDD. The read operation begins when the Word Line signal (WLi ) allows the connection of the core-cell with its two bit lines.

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Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies by Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel


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